The embodiments herein relates to simulation of integrated circuit designs, and more specifically to methods and systems that (if two or more latches of interest have the same state, given the same inputs and environmental conditions) terminate a portion of a simulation associated with a one (or more) of such “same-state” latches and only allow a single portion of the simulation associated with another such “same-state” latch to proceed.
The growing complexity of function and gate counts found in modern digital semiconductor designs has made the verification of those designs the dominant cost of their development and implementation. Design teams rarely have the resources to exhaustively verify their designs, leading to a growing number of bugs not found during the verification process. This area of study includes popular techniques for verifying digital designs, directed random verification, and the diminishing returns which are often cited as the technique's greatest challenge. These diminishing returns are directly related to the inherent redundancy found in directed random verification and the disclosure below explores methods and systems of reducing this redundancy. Methods of optimization commonly create checkpoints at user selected, randomly controlled, decision points and explore the outcomes of these decision points.